Ara es mostren els items 1-20 de 43

  • A cache design for probabilistically analysable real-time systems 

    Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (2013)
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    Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. ...
  • Achieving timing composability with measurement-based probabilistic timing analysis 

    Kosmidis, Leonidas; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (2013)
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    Probabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic ...
  • ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches 

    Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2012)
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    Semiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high ...
  • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation 

    Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown ...
  • Applying measurement-based probabilistic timing analysis to buffer resources 

    Kosmidis, Leonidas; Vardanega, Tulio; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (2013)
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    The use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ...
  • Bus designs for time-probabilistic multicore processors 

    Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
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    Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ...
  • Containing timing-related certification cost in automotive systems deploying complex hardware 

    Kosmidis, Leonidas; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ...
  • Contention in multicore hardware shared resources: Understanding of the state of the art 

    Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Rochange, Christine; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
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    The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ...
  • Control-flow recovery validation using microarchitectural invariants 

    Carretero Casado, Javier Sebastián; Abella Ferrer, Jaume; Vera Gómez, Javier; Chaparro Valero, Pedro Alonso (2011)
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    Processors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new ...
  • Deconstructing bus access control policies for real-time multicores 

    Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...
  • Design of complex circuits using the via-configurable transistor array regular layout fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
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    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...
  • DReAM: Per-task DRAM energy metering in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
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    Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ...
  • DTM: degraded test mode for fault-aware probabilistic timing analysis 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Existing timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ...
  • Efficient cache architectures for reliable hybrid voltage operation using EDC codes 

    Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2013)
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    Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have ...
  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

    González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
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    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...
  • FOCSI: A new layout regularity metric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
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    Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...
  • Fuse: A technique to anticipate failures due to degradation in ALUs 

    Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Unsal, Osman Sabri; Ergin, Oguz; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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    This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder ...
  • Hardware/software-based diagnosis of load-store queues using expandable activity logs 

    Carretero Casado, Javier Sebastián; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Ramírez García, Tanausu; Monchiero, Matteo; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
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    The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing ...
  • Implementing end-to-end register data-flow continuous self-test 

    Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María (2011-08-01)
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    While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort ...
  • Improving early design stage timing modeling in multicore based real-time systems 

    Trilla, David; Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ...