• Control-flow recovery validation using microarchitectural invariants 

    Carretero Casado, Javier Sebastián; Abella Ferrer, Jaume; Vera Gómez, Javier; Chaparro Valero, Pedro Alonso (2011)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Processors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new ...
  • Hardware/software-based diagnosis of load-store queues using expandable activity logs 

    Carretero Casado, Javier Sebastián; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Ramírez García, Tanausu; Monchiero, Matteo; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing ...
  • Implementing end-to-end register data-flow continuous self-test 

    Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María (2011-08-01)
    Article
    Accés restringit per política de l'editorial
    While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort ...
  • Low Vccmin fault-tolerant cache with highly predictable performance 

    Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2009)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent ...
  • Low-cost and efficient fault detection and diagnosis schemes for modern cores 

    Carretero Casado, Javier Sebastián (Universitat Politècnica de Catalunya, 2015-11-18)
    Tesi
    Accés obert
    Continuous improvements in transistor scaling together with microarchitectural advances have made possible the widespread adoption of high-performance processors across all market segments. However, the growing reliability ...
  • Online error detection and correction of erratic bits in register files 

    Vera, Xavier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; González Colás, Antonio María (2009-06)
    Text en actes de congrés
    Accés obert
    Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient ...
  • Selective replication: a lightweight technique for soft errors 

    Vera, Xavier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; González Colás, Antonio María (ACM Press. Association for Computing Machinery, 2009-12)
    Article
    Accés restringit per política de l'editorial
    Soft errors are an important challenge in contemporary microprocessors. Modern processors have caches and large memory arrays protected by parity or error detection and correction codes. However, today’s failure rate is ...