Ara es mostren els items 1-11 de 11

  • A boolean rule-based approach for manufacturability-aware cell routing 

    Cortadella Fortuny, Jordi; Petit Silvestre, Jordi; Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2014-03-01)
    Article
    Accés obert
    An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ...
  • Design guidelines towards compact litho-friendly regular cells 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Elhoj, Martin; Schlinker, Guilherme; Woolaway, Nigel (2011)
    Text en actes de congrés
    Accés obert
  • Lithography aware regular cell design based on a predictive technology model 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2010)
    Text en actes de congrés
    Accés obert
    As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ...
  • Lithography aware regular cell design based on a predictive technology model 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2010-12)
    Article
    Accés restringit per política de l'editorial
    As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ...
  • Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Mauricio Ferré, Juan (2014-07-01)
    Article
    Accés obert
    A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables ...
  • Logic synthesis for manufacturability considering regularity and lithography printability 

    Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inacio (IEEE Computer Society Publications, 2013)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ...
  • Measurements of process variability in 40-nm regular and nonregular layouts 

    Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio (2014-02-01)
    Article
    Accés restringit per política de l'editorial
    As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts ...
  • New redundant logic design concept for high noise and low voltage scenarios 

    García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2011-12)
    Article
    Accés restringit per política de l'editorial
    This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ...
  • On the performance of STDMA Link Scheduling and Switched Beamforming Antennas in Wireless Mesh Networks 

    Gómez Fernández, Sergio (Universitat Politècnica de Catalunya, 2009-09-02)
    Projecte/Treball Final de Carrera
    Accés obert
    Wireless Mesh Networks (WMNs) aim to revolutionize Internet connectivity due to its high throughput, cost-e ectiveness and ease deployment by providing last mile connectivity and/or backhaul support to di erent cellular ...
  • Regular cell design approach considering lithography-induced process variations 

    Gómez Fernández, Sergio (Universitat Politècnica de Catalunya, 2014-10-17)
    Tesi
    Accés obert
    The deployment delays for EUVL, forces IC design to continue using 193nm wavelength lithography with innovative and costly techniques in order to faithfully print sub-wavelength features and combat lithography induced ...
  • Yield estimation model for lithography hotspot distortions 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (Institution of Electrical Engineers, 2013-08-15)
    Article
    Accés restringit per política de l'editorial
    A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield ...