• A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects 

    Jain, Palkesh; Cortadella Fortuny, Jordi; Sapatnekar, Sachin S. (2016-06-01)
    Article
    Accés obert
    A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ...
  • Measurement-based probabilistic timing analysis for multi-path programs 

    Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (2012)
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    Accés restringit per política de l'editorial
    The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
  • Ring oscillator clocks and margins 

    Cortadella Fortuny, Jordi; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés obert
    How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ...
  • Using randomized caches in probabilistic real-time systems 

    Quiñones, Eduardo; Berger, Emery D.; Bernat, Guillem; Cazorla Almeida, Francisco Javier (2009)
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    Accés restringit per política de l'editorial
    While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and ...